The present disclosure relates to a field-effect transistor, a field-effect transistor manufacturing method, a solid-state imaging device, and an electronic apparatus.
Recent years have witnessed progressive refinement of the semiconductor manufacturing technology. This has entailed the problem of increasing off-current due to what is known as the short channel effect in the ordinary planar type transistor structure. As a countermeasure against this problem, studies have been underway to implement a so-called multi-gate structure. This is a structure designed to inhibit the short channel effect using three-dimensional channel regions that enhance the electrostatic control capability of gate electrodes. Explained below in reference to FIGS. 17 through 18B are the major differences between the planar type transistor structure and the multi-gate structure. FIG. 17 shows a typical planar type field-effect transistor, and FIGS. 18A and 18B indicate a field-effect transistor having a fin structure that is one example of the multi-gate structure.
The planar type field-effect transistor shown in FIG. 17 includes a silicon substrate 330, a gate electrode 332 formed on the silicon substrate 330 with a gate insulating file 331 interposed therebetween, and a source region 333 and a drain region 334 formed on the silicon substrate 330 with the gate electrode 332 interposed therebetween.
When an electric field is applied from the gate electrode 332 of the planar type field-effect transistor, a current corresponding to the magnitude of the applied electric field flows the transistor.
FIG. 18A is a perspective view of a fin-structure field-effect transistor, and FIG. 18B is a cross-sectional view of this fin-structure field-effect transistor.
The fin-structure field-effect transistor generally has an insulating layer 340 formed on a substrate (not shown), and an SOI layer that has a source region 341 and a drain region 342 formed with a fin region 343 interposed therebetween on the insulating layer 340. Furthermore, the fin-structure field-effect transistor has a gate electrode 344 formed in a manner surrounding the fin region 343 so that electric fields may be applied thereto in two directions as shown in FIG. 18B.
The fin-structure field-effect transistor above inhibits the short channel effect because it offers the ability to better control currents than the planar type field-effect transistor that has the electric field applied thereto only in one direction.
In addition to the above-outlined fin structure, examples of the multi-gate structure include the tri-gate structure in which electric fields are applied in three directions and the nanowire structure in which the fin region is totally covered with the gate electrode as disclosed by S. Bangsaruntip, et al., IEDM Tech. Dig., p. 297, (2009).